High Performance Buffered X-architecture Zero-skew Clock Tree Construction with via Delay Consideration

As VLSI technology advances into nanometer dimensions, clock routing becomes a limiting factor in determining chip performance. To deal with the challenge, X-architecture has been proposed and widely applied in routing field because it contributes more improvements in terms of the clock delay, wirelength, and power consumption than general Manhattan-architecture. This work proposes an X-architecture zero-skew clock tree construction with buffer insertion/sizing and wire sizing, called a BIS-X algorithm. Differing from other buffer-insertion works, the delay of vias is considered in clock delay calculation. Given a set of n clock sinks with an X-pattern library and a B-type buffer library, an X-pattern matching technique is first used for connecting the paired sinks. Next, two unit-size buffers are respectively inserted into the left and right branches of a tapping point. Then, the inserted buffers are sized for branch delay improvement. Furthermore, X-Flip and wire sizing techniques are sequentially applied for reducing wirelength and keeping zero skew. The proposed BIS-X algorithm can construct a buffered X-architecture zero-skew clock tree level-by-level with minimum delay in O(Bn log n). As reported in the experimental results on benchmarks, our BIS-X averagely reduces clock delay by 32.6%-69.4%, compared with other buffered clock routing algorithms.